Articles with tag "JanHDL"

• Fixing Verilog is easy 2023-06-06
• Wasting real time in zero time 2023-06-06
• Pitfalls for circuit girls 2023-06-06
• Time for reflection 2019-07-08
• VHDL's crown jewel 2023-06-06
• Verilog's major flaw 2023-06-06
• Your favorite mistake 2019-05-17
• EDA 2.0 2019-06-26
• The most needed EDA innovation 2019-05-17
• The biggest EDA innovations that did not happen 2019-07-08
• The latest EDA innovation: logic synthesis! 2019-05-17
• Academic frustration 2019-07-08
• Synthesis was my first love 2019-07-08
• A 20-year old relationship 2019-05-17
• [Announce] Jan on HDL Design 2019-08-29