How to set up the UVM Library in Sigasi Visual HDL

How to Set Up the UVM Library in Sigasi Visual HDL

Introduction

The UVM  (Universal Verification Methodology) library is a standard framework for creating reusable verification components and building structured, scalable testbenches in SystemVerilog. It is widely used in FPGA and ASIC verification environments. UVM simplifies the verification process and enhances productivity by promoting a standardized approach to building test environments.

In this guide, we will walk you through the steps required to integrate the UVM library into a Sigasi Visual HDL project. The process involves compiling UVM into the Library Database and adding it to the Common Libraries of your project.

Prerequisites

1. Download the UVM library from a trusted source, such as the official Accellera website , or locate it within your simulation tool’s installation directory. Typically, UVM is included with simulators like QuestaSim, VCS, or Xcelium.
2. Open the project you want to add UVM support to, or create a new project.

Adding UVM to the Library Database

1. Open the VS Code command palette (Ctrl+Shift+P) and type to select Sigasi: Open Tools and Libraries Settings.

2. Click ADD… and navigate to the directory containing the UVM library files.

   • Point to the root folder of the UVM library. It should contain a src directory. Within that directory, the file uvm_pkg.sv should be present.
   • The library type should be detected as UVM. If it is not detected automatically, verify that the directory contains src/uvm_pkg.sv or troubleshoot the directory structure.

3. Press Extract. The UVM library will now be compiled into the Library Database.

You can repeat this process for multiple versions of the UVM library, provided each version has a unique alias in the Library Database.

Adding the UVM Library to the Project

1. Open the project preferences: right-click on the project in the Sigasi Projects view and select Configure > Open Project Preferences.

2. Choose Common Libraries in the sidebar.

3. Enable the UVM library from the list of libraries.

   If multiple versions of UVM exist in the Library Database, select the appropriate version in the Active Tools and Libraries section. To learn more about third-party library management in Sigasi, click here.

Conclusion

The UVM library is now correctly set up in Sigasi Visual HDL. To verify that everything works, add the following file to your project. If no issues are reported, the setup is complete.

`include "uvm_macros.svh"
import uvm_pkg::*;

module uvm_tb;

    initial begin
        uvm_report_info("UVM Test", "Starting simulation", UVM_LOW);
        $finish;
    end

endmodule

Congratulations! You’re now ready to utilize the UVM library in your verification environment.