How to set up the UVVM Library in Sigasi Visual HDL

Introduction

UVVM  (Universal VHDL Verification Methodology) is an open-source framework designed to streamline the creation of structured VHDL testbenches, facilitating the verification of FPGA and ASIC designs. It provides a comprehensive library of verification components and utilities to help design teams reduce the effort and complexity involved in writing testbenches.

In this guide, we will walk you through the steps required to integrate the UVVM framework into a Sigasi Visual HDL project. The process involves compiling UVVM to the Library Database and then adding it to the Common Libraries of your project.

Prerequisites

1. Download the desired version of the framework from GitHub . Extract the archive or clone the repository to a directory of your choice.
2. Open the project that you want to add UVVM support to, or create a new project. Make sure the project is configured to use VHDL 2008.

Adding UVVM to the Library Database

1. Open the VS Code command palette (Ctrl+Shift+P) and type to select Sigasi: Open Tools and Libraries Settings.

2. Click ADD… and navigate to the directory containing the UVVM library.

   The library type should be detected as UVVM automatically. If it isn’t, verify that the directory includes the uvvm_vvc_framework folder.

3. Press Extract. The UVVM framework will now be compiled into the Library Database.

You can repeat this process for every version of UVVM that you intend to use. The library database can contain multiple versions of UVVM, as long as they have a unique alias.

Adding the UVVM Library to the Project

1. Open the project preferences: right-click on the project in the Sigasi Projects view and select Open Preference View.
2. Choose Common Libraries in the sidebar.
3. Enable the UVVM library from the list of libraries.

If multiple versions of UVVM exist in the library database, select the appropriate version in the Active Tools and Libraries section. To learn more about 3rd party library management in Sigasi click here.

Conclusion

The UVVM framework is now correctly set up in Sigasi Visual HDL. To verify that everything works, add the following file to your project. If no issues are reported, the setup is complete.

library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_sbi;
context bitvis_vip_sbi.vvc_context;

entity uvm_tb is
end entity uvm_tb;

architecture RTL of uvm_tb is
begin
    p_main : process is
    begin
        log("Starting simulations");
        std.env.stop;
        wait;
   end process p_main;
end architecture RTL;

Congratulations! You’re now all set to unleash the power of the UVVM framework and take your design verification to the next level.