Sigasi Linting Rules

The main documentation on linting rules and how to configure them is available through the following links.

Sigasi Visual HDL

Linting and Quick Fixes
VHDL Linting
Verilog and SystemVerilog Linting
UVM Linting Rules

Sigasi Visual HDL for Eclipse

Linting and Quick Fixes
VHDL Linting
Verilog and SystemVerilog Linting
UVM Linting Rules

The following chapters contain detailed explanations for the various linting rules.

Avoid using general purpose 'always'
Capitalization of Identifiers
Case Alternative Contains Duplicate Choices
Check for Component/Entity Mismatch
Check Header Comment
Clock Signal Not Used as Clock
Comparison of Vectors with Different Sizes
Cyclic class inheritance
Dead Code Linting Rule
Deep nesting of conditional and loop statements
Deep Nesting of Conditional and Loop Statements
Deprecated IEEE Packages and Non-Standard Packages
Deprecated UVM API
Duplicate Signal in Sensitivity List
End Name Does Not Match Declaration Name
End name not allowed
End name without begin name
Filename Contains Primary Unit Name
Illegal Mode View Element Mode
Implicit Vector to Boolean Conversion
Include of globally available declaration
Incomplete Port Maps and Generic Maps
Incomplete Reset Branch
Inconsistent Clock Edge Usage
Inconsistent Reset Style
Incorrect Constructor for UVM Object or Component
Incorrect Override of UVM Object
Incorrect Utility Macro
Incorrect UVM Object Instantiation
Incorrect Vector Range Direction
Language Feature Restrictions
Linting Rules for Arrays
Linting Rules for Deferred Constants
Linting Rules for Design Unit Locations
Linting Rules for Instances
Linting Rules for Loops
Locally unused port, argument or parameter …
Missing include path in preprocessor configuration
Missing Label
Missing Mode for Record Element in Mode View
Mixing statement and block name
Multiple Objects in One Declaration
Names differing only by case
Naming Conventions
Null or Empty Range
Order of Associations
Order of named declaration list does not match
Positional Association in Instantiations
Prohibited Macro
Redundant "others"
Sensitivity List
Space Before the Physical Unit
Superfluous Library Clause
Testing Equality of Booleans to true or false
Tool Compatibility Rules
Type Argument Value Does Not Match Containing …
Types in Expressions
Unconstrained Signal or Variable of Integer Type
Unexpected Clock Edge Specification
Unexpected content following directive
Unexpected FSM State Type
Unexpected Keyword Capitalization
Unexpected Output System Task
Unregistered UVM Object
UVM Object Name Does Not Match Variable Name
UVM Phase Method Does Not Call Superclass Method
Vector as Edge Event Expression
Vector Width in Assignments and Port Maps
Verilog Ambiguous Reference
Verilog Assignment Patterns
Verilog Case Statements
Verilog Checks on Initialization
Verilog Class Item Visibility
Verilog Coding Style
Verilog Duplicate Conditions
Verilog Duplicate Continuous Assignments
Verilog Duplicate Declaration
Verilog Duplicate Port
Verilog Empty Assignment Pattern
Verilog Empty Concatenation
Verilog Empty Parameters
Verilog Empty Port
Verilog Empty Port in ANSI Port List
Verilog Functions
Verilog Hiding Non-virtual Methods
Verilog Identifiers and Data Types
Verilog Implicit Net
Verilog Incorrect Port Declaration
Verilog Inputs
Verilog Keywords in VHDL
Verilog Out-of-bound Method Declarations
Verilog Overridden Method Signatures
Verilog Parameters
Verilog Port and Parameter Associations
Verilog Processes
Verilog reg and logic Datatype
Verilog Type Checking
Verilog Unused Declaration
Verilog Unused Macros
Verilog Upward Reference
VHDL Coding Style Rules
VHDL Language Version

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