Sigasi Visual HDL can check that the same clock edge is used throughout the entire design. It provides a clean coding style simplifying maintainability and enhancing safety. If using a single edge is too restrictive, this rule can be configured to check the clock edge usage consistency for each design file. This rule consists of three check types:
- rising, ensures that all clock edges are rising edges
- falling, ensures that all clock edges are falling edges
- consistent, adapts the rule to the most used edge per design file. If there are equal amounts of rising and falling edges, the first encountered edge will be chosen
The default configured type is consistent, but this can be changed in the Errors/Warnings project setting or workspace preference.
Example with rising edge selected
process(clk) is
variable count : natural := 0;
begin
if rising_edge(clk) then
count := count + 1;
end if;
if falling_edge(clk) then -- Inconsistent!
count := count - 1;
end if;
end process;
Note that this rule also works with the old-school clock edge condition:
process(clk) is
variable count : natural := 0;
begin
if clk'event and clk = '1' then
count := count + 1;
end if;
if clk'event and clk = '0' then -- Inconsistent!
count := count - 1;
end if;
end process;
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
254/severity/${path}={error|warning|info|ignore}
254/params/expected_edge/${path}={consistent|rising|falling}