Unexpected Clock Edge Specification

Sigasi Visual HDL can check that the same clock edge specification style is used throughout the entire design. This standard rule provides a clean coding style guaranteeing consistency in clock checks. This rule consists of three configurable options:

• event attribute, ensures that all clock conditions are using the event attribute, for example, clk'event and clk = '1'
• stable attribute, ensures that all clock conditions are using the stable attribute, for example, not clk'stable and clk = '1'
• edge function (the default), ensures that all clock conditions are using an edge function, for example, rising_edge(clk) falling_edge(clk)

Example with “edge function” selected

process(clk) is
    variable count : natural := 0;
begin
    if clk'event and clk='0' then -- Wrong clock style!
        count := count + 1;
    end if;
end process;

process(clk) is
    variable count : natural := 0;
begin
    if falling_edge(clk) then
        count := count - 1;
    end if;
end process;

Note that using clock attributes is deprecated since VHDL 93 by the IEEE 1164 standard, use edge functions instead.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

250/severity/${path}={error|warning|info|ignore}
250/params/style/${path}={edge_function|stable_attribute|event_attribute}