Sigasi Visual HDL (SVH) warns about incomplete port maps, generic maps, and parameters in an argument list: Port map uses default values. Missing optional actuals: yourport
Input ports, generics and parameters need to be assigned in your instantiation statement if they don’t already have a default value. If you don’t do this, you are writing illegal VHDL. SVH will mark an error, and so will all other tools.
Input ports, generics and parameters with a default value, as well as output ports, do not need to be assigned explicitly. However, this is often not intended. For that reason, SVH can warn you about this.
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
94/severity/${path}={error|warning|info|ignore}