Order of Associations

Sigasi Visual HDL gives a warning when the order of generics, ports, or parameters in a map or subprogram argument list differs from their original declaration order.

architecture RTL of dut is

   component my_comp port (
      clk  : in  std_logic;
      rst  : in  std_logic;
      inp  : in  std_logic;
      outp : out std_logic);
   end component;

begin
   assert iterations <= MAX_COUNT;

   i_comp_1: my_comp port map( -- associations should be kept in the same order as the declaration
      rst  => rst,
      clk  => clk,
      inp  => data_in(0), 
      outp => open
   );

   i_comp_1: my_comp port map(
      clk  => clk, 
      rst  => rst,
      inp  => data_in(0), 
      outp => open
   );

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

177/severity/${path}={error|warning|info|ignore}