Sensitivity List

Sigasi Visual HDL can warn about problems with your sensitivity list:

Presence of either a sensitivity list or one or more wait statements in a process

VHDL requires a sensitivity list for each process or wait statements in the process body.

Incomplete sensitivity list

A sensitivity list should contain all signals the process is sensitive to.

process(a)
begin
   c <= a and b;
end process;

Superfluous signals in sensitivity list

A sensitivity list should only contain signals the process is sensitive to. Adding more signals will only slow down your simulations.

process(a, b, c)
begin
   c <= a and b;
end process;

Duplicate signals in sensitivity list

A sensitivity list should only contain signals the process is sensitive to. Adding duplicate signals is likely a typo and doesn’t have any practical effect.

process(a, b, b)
begin
   c <= a and b;
end process;

A sensitivity list should contain all signals that are read asynchronously in the process. For a combinatorial process, all signals read by the process should be in the sensitivity list. For a synchronous or clocked process, only the clock signal and an asynchronous reset signal (if present) should be in the sensitivity list. In synthesizable code, an incomplete sensitivity list will likely cause a synthesis-simulation mismatch. Even in test benches and purely behavioral code, an incomplete sensitivity list is often unintended and may lead to an unexpected simulation result. Most synthesis tools ignore the sensitivity list. In traditional workflows, only the synthesis warnings will give you a hint that your sensitivity list is incomplete. This report will be available only hours or even days after you have finished typing your code. Flagging this problem early can save a lot of time.

Since VHDL-2008, you can write process (all) to make sure you have all the necessary signals in the sensitivity list.

process(a, b)
begin
   c <= a and b;
end process;

process(clk)
begin
   if rising_edge(clk) then
      -- code
   end if;
end process;

process(clk, rst)
begin
   if rst = '1' then
      -- reset code
   elsif rising_edge(clk) then
      -- code
   end if;
end process;

process(all)
begin
   c <= a and b;
end process;

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured with the following template:

38/severity/${path}={error|warning|info|ignore} # Neither sensitivity nor wait
72/severity/${path}={error|warning|info|ignore} # Incomplete sensitivity list
73/severity/${path}={error|warning|info|ignore} # Superfluous signals
85/severity/${path}={error|warning|info|ignore} # Duplicate signals