Vector Width in Assignments and Port Maps

Sigasi Visual HDL (SVH) checks the vector size in assignments and port maps. This check works at type-time and takes the (symbolic) value of generics into account.

SVH will not take into account the value assigned to a generic in instantiations. The reasoning behind this is explained here.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

144/severity/${path}={error|warning|info|ignore}