Deeply nested conditional and loop statements reduce code readability. Restructuring code or extracting logic to functions can help to keep code in a maintainable state.
Another problem is that deep nesting can result in complicated prioritized logic being synthesized increasing circuit size significantly.
Sigasi Visual HDL can report deeply nested sequential loops and conditions. Note that this rule has the maximum nested depth set to 5
and is ignored by default. You can enable it in the Verilog Errors/Warnings preference page (Style Validation > Deep nesting of conditional and loop statements).
Example with a nesting limit of 2:
module m;
int x;
task foo();
x = 5;
if (x > 0) begin
if (x > 1) begin
if (x > 2) begin // nesting depth 2
if (x > 3) begin
$display("x is greater than 3");
end
end
end
end
endtask
endmodule
Example of conditional generate constructs with a nesting limit of 1:
module m;
if (0)
if (1)
begin
// do something
end
else if (2)
begin
// do something
end
else ; // empty
endmodule
Example A long chain of else-if constructs does not count as nesting even though it technically is, because it’s very readable and commonly used:
module m; always_comb begin if (1) $display(1); else if (2) $display(2); else if (3) $display(3); else if (4) $display(4); else if (5) $display(5); else if (6) $display(6); else if (7) $display(7); end endmodule
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
167/severity/${path}={error|warning|info|ignore}
167/params/limit/${path}=${integer}
167/params/check_conditional_generate_constructs/${path}={true|false}