Verilog Empty Port

When using the non-ANSI style, it is legal to have empty ports in the port list. An empty port will be translated to an anonymous port that nullifies anything connected to it. Such empty ports are usually the result of superfluous commas and rarely reflect the intended design. Empty ports are marked as warnings by Sigasi (rule 142).

module discouraged_code(
    a,
    ,
    b
);
    input a;
    output b;
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

142/severity/${path}={error|warning|info|ignore}