Verilog Functions

Non-blocking assignments are not allowed in functions

A non-blocking assignment (<=) is not allowed in a (System)Verilog function. While syntactically correct, it will generally not lead to the desired behavior, and will likely cause synthesis-simulation mismatch. Sigasi Visual HDL (SVH) flags an error if a blocking assignment is used in a function (rule 41).

A good fix to correct the problem is to replace non-blocking assignments (<=) with blocking assignments (=)

module badcode;
	function plus_one;
		input integer a;
		begin
			plus_one <= a + 1;  // Incorrect: non-blocking assignment
		end
	endfunction
endmodule

module goodcode;
	function plus_one;
		input integer a;
		begin
			plus_one = a + 1;   // Correct: blocking assignment
		end
	endfunction
endmodule

Function prototype has implicit return type

SystemVerilog function prototypes (pure virtual functions) should have a return type. SVH warns for function prototypes without return type (rule 10).

virtual class badclass;
    pure virtual function myfunc(input bit[31:0] data);           // return type missing
endclass

virtual class goodclass;
    pure virtual function integer myfunc(input bit[31:0] data);
endclass

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured with the following template:

41/severity/${path}={error|warning|info|ignore} # Non-blocking assignment in function
10/severity/${path}={error|warning|info|ignore} # Function prototype with implicit return type