Names differing only by case

Using names that differ only by case is not desirable, even if this is valid in Verilog. This can be confusing, or it may have been a mistake on the part of the original developer.

Avoiding such mistakes improves readability, prevents potential issues, and encourages a good style.

Sigasi Visual HDL can report this as a warning.

class my_class;
    // class definition
endclass

class MY_CLASS;
    // class definition
endclass

module m;
    int abc = 1;
    int Abc = 1;
    int ABC = 1;
    int s = abc + Abc + ABC;
    $display("Sum = %0d", s);
endmodule

Rule Configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

166/severity/${path}={error|warning|info|ignore}