Even though the Verilog specification does not allow additional trailing content on lines with preprocessor directives, many tools allow this. The non-standard compliant content is marked with a warning.
`include "warning.svh"; // Trailing content in directive line `include "ok.svh" ; // Insert a newline after the directive to comply with the specification
It is recommended that you fix these problems since they are not covered by the Verilog standard.
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
156/severity/${path}={error|warning|info|ignore}