Unbound component instantiation

Omitting explicit bindings for component instantiations in VHDL configurations can introduce ambiguity and errors into your design, making the source code harder to read and maintain. Explicitly binding component instantiations clarifies the intended design hierarchy and helps ensure correct component usage.

This linting rule identifies component instantiations in VHDL configurations that do not have explicit bindings.

architecture rtl of processor is
    component alu is
        port (
            op     : in  std_logic_vector(1 downto 0);
            A, B   : in  std_logic_vector(7 downto 0);
            result : out std_logic_vector(7 downto 0)
        );
    end component;
begin
    U1: alu port map (
        op     => op,
        A      => A,
        B      => B,
        result => result
    );
end rtl;

configuration cfg_processor_behavioral of processor is
    for rtl
    end for;
end cfg_processor_behavioral;

Rule Configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

48/severity/${path}={error|warning|info|ignore}