Templates Editor
The templates editor allows you to define reusable code blocks encompassing frequently used elements like process blocks, signal declarations, or loop constructs. You can seamlessly insert these templates into your VHDL or Verilog code at the cursor position. This eliminates the need for manual typing of repetitive structures, saving you valuable time and reducing the potential for inconsistencies.
You can access the editor through the preferences (search for sigasi.userDefinedTemplates). The preference you’ll find has a button to edit your custom templates. It is also available through Ctrl + Shift + P > Sigasi: Open Templates Editor.
Template Variables
In templates you can use variables whose values will be resolved at the time of insertion. Some variables have arguments that require an ID in order to be used, for example ${path:env('PATH')}.
The following is a list of all built-in variables SVH supports:
| Variable | Description |
|---|---|
${cursor} | Specifies where the cursor will end up when the template is completed. |
${date}${id:date(format[,locale])} | Evaluates to the current date in the specified format and locale. The format and locale parameters are optional. |
${dollar} | Evaluates to the dollar symbol $. Alternatively, $$ can be used. |
${id:env(name)} | Evaluates to the specified enviromnent variable. |
${filename} | Evaluates to the name of the file. |
${filename_ext} | Evaluates to the extension of the file. |
${user} | Evaluates to the user name. |
${year} | Evaluates to the current year. |
Importing Templates from SVH in Eclipse
If you previously used SVH in Eclipse, you can transfer any custom templates you created there to the SVH Extension for VSCode:
- Export the custom templates as an XML file from within SVH in Eclipse.
- Import the XML file(s) into the SVH Extension from the Templates Editor, or by using Sigasi: Import Eclipse Templates from the Command Palette.
