Focus shifts for HDL workflow in chiplet era

Sigasi Highlighted in Electronics Weekly

During DAC61 , held at the end of June 2024, Caroline Hayes of Electronics Weekly spoke with Sigasi’s Dirk Seynhaeve, about how the new Sigasi® Visual HDL™ seeks to optimize the HDL workflow.

From the Article

DAC 2024: The need to organise HDL hardware description language) tools in an era of chiplet design and higher abstraction and higher synthesis levels, Sigasi has introduced its Visual HDL portfolio, designed to correct inefficient HDL-based design workflows and reduce the number of iterations needed.

Click here to read the full article at Electronics Weekly. 

2024-07-01, last modified on 2024-11-27