Developing Workflows to Streamline System-Level Design

Third Installment of System-Level Design “Experts at the Table” Published by Semiconductor Engineering

Sigasi’s VP for Business Development, Dirk Seynhaeve, joined colleagues from Arteris, Keysight, Siemens EDA, and Synopsys for a round table discussion about the future of system-level design, hosted by Semiconductor Engineering.

In the first two parts of the conversation, which you can read here and here, the group considered how the design process will become increasingly more workflow- and work-load specific given the rise in chip complexity.

This third and final installment, titled “Developing Workflows to Streamline System-Level Design,” gets into the specifics of how EDA tool creators and providers (like Sigasi!) can show customers what’s possible.

From the Article

One of the big challenges facing EDA companies is explaining to customers what’s possible, how to streamline their designs, and what can be accomplished at what level of risk.

Click here to read the entire article at Semiconductor Engineering. 

2024-09-05, last modified on 2024-09-25