All Articles

• Synthesis was my first love 2025-02-21
• Academic frustration 2025-02-21
• The latest EDA innovation: logic synthesis! 2025-02-21
• The most needed EDA innovation 2025-02-21
• EDA 2.0 2025-02-21
• Your favorite mistake 2025-02-21
• Verilog's major flaw 2025-02-21
• VHDL's crown jewel 2025-02-21
• Time for reflection 2025-02-21
• Pitfalls for circuit girls 2025-02-21
• Wasting real time in zero time 2025-02-21
• Fixing Verilog is easy 2025-02-21
• A 20-year old relationship 2024-11-27
• [Announce] Jan on HDL Design 2024-11-21
• The biggest EDA innovations that did not happen 2019-07-08