A 20-year old relationship

Next year, in 2010, my relationship with VHDL will be 20 years old. It has been a good journey, but I can’t say that it was love at first sight.

The first chip I designed while at Alcatel was done with Verilog. I remember that I was quite happy with Verilog. However, at the time (1990) there was this idea that very soon VHDL would take over the whole market. I remember very well how that idea was cultivated by a start-up CAD company called Synopsys.

At a certain point, management decided to switch to VHDL. So I promptly wrote a memo explaining why that decision was wrong, and why Verilog would prosper, using the kind of pro-Verilog arguments that I have been reading over and over again since. I believe that is why I understand the pro-Verilog camp well: I was once part of it.

Over the years my relationship with Verilog deteriorated into a love-hate relationship that eventually ended with a separation with mutual consent. I just had too many bad surprises. I often felt that Verilog was like a nice looking building on very shaky foundations. Therefore, I eventually settled for the solid ground of VHDL’s strong typing and delta cycle algorithm.

In retrospect, the pro-Verilog analysis in my memo to management wasn’t wrong. Verilog really has prospered, even though the building doesn’t look nice anymore because of too many additions from too many architects. However, management’s decision to switch to VHDL wasn’t wrong either. VHDL has prospered too.

Late 1991, I co-founded a design services company called easics , and we faced the choice between Verilog and VHDL. Our strong point was a methodology based on the vision that I presented in my previous blog post: digital hardware design is a kind of software development. We concluded that VHDL was a better language to support that vision. And in fact, VHDL has kept its promises and things have turned out pretty well. VHDL has been a good choice for us.