The latest EDA innovation: logic synthesis!

A few months ago Richard Goering blogged about the 5 greatest moments in EDA innovation. Here is the list: Spice, Verilog, Multi-level logic synthesis, Automated IC layout and Structured VLSI design.

I would make some minor edits to the list. Instead of Verilog, I would nominate VHDL and Verilog, because I believe we have at least as much to thank to VHDL as to Verilog. Instead of multi-level logic synthesis, I would list RTL synthesis, because that has been the standard for digital design standard during the last 20 years. It builds on logic synthesis by adding the concept of synthesizing from clocked hardware descriptions written in a hardware description language.

On a sidenote, it’s kind of funny that Mr. Goering mentions a lot of synthesis technology contributors, but not Synopsys, the company that made it all happen. But OK, that’s Cadence company policy I guess.

Overall, I agree with the list. Its most remarkable feature is that all these great innovations are quite old. By 1985, the year I graduated as an engineer, the fundamental research and development for all of them had been done. By 1990, the year I became a hardware designer for real, all were well-established solutions. In fact, if the list would have been compiled 15 years ago, I think it would have been exactly the same.

The youngest of these innovations is logic synthesis. This confirms my experience that it was a one-of-a-kind innovation, as I testified in “[synthesis-was-my-first-love]”. However, it also means that nothing as great has happened in EDA during my career as a digital hardware designer.

That is certainly not what I expected on my graduation day. Back in 1985, there was a feeling of great enthusiasm about digital VLSI design and about EDA as its prime enabler. It looked like a vast unexplored field with lots of exciting innovations waiting to happen. It’s quite a shock to realize that the greatest moments were in fact already behind us.