Working with preprocessors can be frustrating. Includes and macro expansions are very powerful; but if you make any typo, figuring out what went wrong can be really painful.
In this video you will learn how Sigasi can help you write and understand preprocessor code like macro’s and defines with flair.
The Preprocessor View is documented here.
See also
- Cross project includes in SystemVerilog (legacy)
- Configure include paths in Sigasi Visual HDL for Eclipse (screencast)
- Autocompletes for Verilog and SystemVerilog defines and includes (screencast)
- Case statements in VHDL and (System)Verilog (blog post)
- Checking case statements in SystemVerilog (screencast)